1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to an improvement in a bidirectional triode thyristor.
2. Description of the Prior Art
FIG. 1 is a sectional view typically showing the structure of a conventional bidirectional triode thyristor (hereinafter referred to as "TRIAC"), which is well-known in the field of semiconductor devices. Referring to FIG. 1, a p-type first base layer 2 is formed on a first major surface 101 of an n-type semiconductor layer 1, which is prepared as a semiconductor substrate, for example. An n-type first emitter layer 4 is formed in a part of the surface of the first base layer 2, and an n-type gate portion emitter layer 10 is formed in another part of the surface of the first base layer 2. A p-type second base layer 3 is formed on a second major surface 102 of the semiconductor layer 1, and an n-type second emitter layer 5 is formed in a part of the surface of the second base layer 3. An end portion 1b of the semiconductor layer 1 is formed to enclose the side surface of the first base layer 2. Further, an end portion of the second base layer 3 is formed as an isolation region 3a enclosing the side surface of the semiconductor layer 1. A first main electrode layer 6 is formed over the surface of the first base layer 2 and the first emitter layer 4. A gate electrode layer 9 is formed over the surfaces of the first base layer 2 and the gate portion emitter layer 10. A second main electrode layer 7 is formed over the surfaces of the second base layer 3 and the second emitter layer 5. In such a TRIAC, the first main electrode layer 6 is generally called T.sub.1 electrode, and the second main electrode layer 7 is called T.sub.2 electrode.
It is assumed here that V.sub.1 represents voltage applied to the first main electrode layer 6 (T.sub.1), V.sub.2 represents voltage applied to the second main electrode layer 7 (T.sub.2) and V.sub.G represents voltage applied to the gate electrode layer 9 (T.sub.G). It is well known that a TRIAC has the following four trigger modes expressed by relations between V.sub.1, V.sub.2 and V.sub.G :
Mode I: V.sub.1 &lt;V.sub.2, V.sub.1 &lt;V.sub.G PA1 Mode II: V.sub.1 &lt;V.sub.2, V.sub.G &lt;V.sub.1 PA1 Mode III: V.sub.2 &lt;V.sub.1, V.sub.G &lt;V.sub.1 PA1 Mode IV: V.sub.2 &lt;V.sub.1, V.sub.1 &lt;V.sub.G
Transverse resistance of the first base layer 2 exerts influence on the value of gate trigger current, which flows to the gate electrode layer 9 in triggering.
When the voltage V.sub.G is higher than the voltage V.sub.1 in the mode I or IV, gate trigger current I.sub.G1 flows from the gate electrode layer 9 to the first main electrode layer 6 through the first base layer 2. At this time, voltage drop .DELTA.V.sub.1 is caused by transverse resistance R.sub.2a in a region 2a, which is a part of the first base layer 2 existing under the first emitter layer 4, and the gate trigger current I.sub.G1. .DELTA.V.sub.1 is equal to I.sub.G1 R.sub.2a. The voltage drop .DELTA.V.sub.1 increased the potential at the region 2a to be higher than that of the first emitter layer 4. Consequently, a p-n junction J.sub.3 between the region 2a and the first emitter layer 4 is forward-biased so that electrons are injected into the semiconductor layer 1 from the first emitter layer 4 through the region 2a, i.e., through the first base layer 2. Thus, triggering of the TRIAc is started so that current flows between the first main electrode layer 6 and the second main electrode layer 7, the direction of the current being determined in accordance with the sign of the difference between the voltage V.sub.1 and the voltage V.sub.2.
When, on the other hand, the voltage V.sub.1 is higher than the voltage V.sub.G in the mode II or III, gate trigger current I.sub.G2 flows from the first main electrode layer 6 to the gate electrode layer 9 through the first base layer 2. At this time, voltage drop .DELTA.V.sub.2 is caused on by transverse resistance R.sub.2b of a region 2b, which is a part of the first base layer 2 existing under the gate portion emitter layer 10, and the gate trigger current I.sub.G2. .DELTA.V.sub.2 is equal to I.sub.G2 R.sub.2b. Consequently, a p-n junction J.sub.5 between the region 2b and the gate portion emitter layer 10 is forward-biased so that electrons are injected into the semiconductor layer 1 from the gate portion emitter layer 10 through the region 2b, i.e., the first base layer 2. Thus, triggering of the TRIAC is started.
As hereinabove described, the voltage drop .DELTA.V.sub.1 or .DELTA.V.sub.2 caused by the gate trigger current I.sub.G1 or I.sub.G2 and the transverse resistance R.sub.2a or R.sub.2b of the first base layer 2 is utilized in each of the four trigger modes.
For the purpose of improving sensitivity of the TRIAC, reduction of the gate trigger current I.sub.G1 or I.sub.G2 is required. The transverse resistance R.sub.2a or R.sub.2b, i.e., specific resistance of the first base layer 2 may be increased in order to obtain the voltage drop .DELTA.V.sub.1 or .DELTA.V.sub.2 of a prescribed level with smaller gate trigger current. However, such increase in specific resistance of the first base layer 2 degrades other principal characteristics such as voltage proof and commutation characteristic, etc.
On the other hand, transverse resistance R.sub.3 of the second base layer 3 exerts influence on the value of gate trigger current in the modes III and IV, as hereafter described. First, electrons are injected into the semiconductor layer 1 from the first emitter layer 4 or the gate portion emitter layer 10 through the first base layer 2 by the aforementioned trigger starting operation. As a result, a p-n junction J.sub.2 between the first base layer 2 and the semiconductor layer 1 is forward-biased so that positive holes are injected into the second base layer 3 this time from the first base layer 2 through the semiconductor layer 1. The positive holes thus injected into the second base layer 3 reach the second main electrode layer 7. At this time, voltage drop .DELTA.V.sub.3 is caused by positive-hole current I.sub.3 and the transverse resistance R.sub.3 in a region 3b, which is a part of the second base layer 3 existing under the second emitter layer 5. .DELTA.V.sub.3 is equal to I.sub.3 R.sub.3. The voltage drop .DELTA.V.sub.3 forward-biases a p-n junction J.sub.4 between the second base layer 3 and the second emitter layer 5. As the result, injectoin of electrons from the second emitter layer 5 to the second base layer 3 is started to allow conduction of the TRIAC.
As hereinabove described, the voltage drop .DELTA.V.sub.3 based on the current I.sub.3 and the transverse resistance R.sub.3 in the region 3a is utilized in the modes III and IV. The current I.sub.3 is generated on the basis of the gate trigger current I.sub.G1 or I.sub.G2 as hereinabove described. Therefore, the transverse resistance R.sub.3, i.e., specific resistance of the second base layer 3 may be increased in order to reduce the gate trigger current I.sub.G1 or I.sub.G2 for the purpose of improving sensitivity of the TRIAC. However, such increase in specific resistance of the second base layer 3 disadvantageously degrades other principal characteristics such as the commutation characteristic.